This page mainly refers to the Type 3 DMA controller.
There is a Type 1 and Type 2 DMA controller also. Early MCA DMA system
implementations had a 24 bit address limit and cannot access more than
16MB of memory (Type 1 and Type 2 complexes). With Type 3 and above complexes
(32 bit DMA), up to 4GB of memory can be addressed.
The Direct Memory Access (DMA) controller uses eight channels
to manage the transfer of data between two addressable locations within
DMA channels 0 and 4 are active in MCA systems and can
be reprogrammed by an OS to respond to arbitration levels 8 thru 15. This
dynamic reassignment ability allows up to 15 slave DMA devices to be supported
on the 8 channel DMA controller.
Although 8 concurrent DMA data transfers may be active
at the same time, the data does not move simultaneously. This is because
only one DMA controller can take over the bus at a time.
Arbitration and Virtual DMA
Each DMA port is assigned an arbitration level to which
it responds when that level recieves control of the bus. The arb level
is set in a 4 bit POS register during setup. DMA levels 0-7 are assigned
to arb levels 0-7 during boot.
In MCA systems, the channel assignments can be dynamically
changed. DMA levels 0 and 4 are assigned as virtual DMA levels. Levels
1-3 and 5-7 are fixed in their arb levels (for compatibility with software
for older systems) but the processing routines can sort through the available
DMA channels when a request is made for a DMA operation
If a device requests a specific DMA channel, the DMA controller
looks for any available channel and carries out the task. The controller
then replies to the requesting device that the DMA function has been served
on the DMA channel that the device demanded.
Arb Level -2
Used to perform memory refresh
Arb Level -1
Allows the system processor to gain control of the bus.
If there is an active transfer occuring, the system processor will take
over after it's finished. Any pending transfers are preempted until the
system processor finishes.
Arb Level 2
Reserved for the floppy controller.
Arb Level F
Reserved for the system processor
Supported DMA operations are data-transfer and memory-verify.
Data-transfer moves data between an I/O device and memory, while the memory-verify
performs a memory read cycle but no write cycle.
The DMA controller uses two interfaces to control DMA
operations: programmed I/O (PIO) and subsystem control block (SCB). In
PIO mode, the DMA controller supports a 24 bit memory address and an 8
or 16 bit data width. In the SCB mode, the DMA controller supports 32 bit
addressing and 8, 16, and 32 bit data widths using control blocks.
A set of programmable registers are used to setup each
channel and to manage the transfer. Each channel has it's own 24 bit memory
address register and 16 bit transfer counter to define each DMA operation.
Data width for each transfer is either 8 or 16 bits and is determined by
the width of the participating devices.
Each channel responds to an arbitration level equal to
it's channel number. The arbitration levels for DMA channels 0 and 4 are
programmable and can be modified to other arbitration values.
Registers are used to setup each channel; control blocks
are then used to manage the transfer operation.
The control block specifies the type of operation, the
source and destination addresses of the data, and other parameters. The
source or destination addresses can point to a data location or toan indirect
list that points to several locations. The width of each transfer is either
8, 16, or 32 bits and is determined dynamically by signal protocols on
the system channel. All channels support 32 bit memory addressing, 32 bit
transfer counts, and data chaining.
Each DMA channel has a local arbiter that can be programmed
independently to request the system channel and arbitrate for a device.
Note: The Server 95 DMA controller
supports a programming model and register set that is compatible with the
DMA controller used in AT-bus systems. Although the DMA controller maintains
some compatibility with this interface, new programs should use either
the PIO or SCB interface.
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