@8f6d.adf  IBM Ethernet Quad-BT PeerMaster (RJ45) 
C8f6d.adf  ADP for BT 

Peermaster MCA for OS2, NW, Netfinity and NT   Drivers, utils 
194-358 Ethernet Quad Peermaster Adapter
Installation Manual In *.eps or email me for Peermaster.pdf

Peermaster
ADF Sections
LED Indications

D5  LED is normally off prior to adapter download, and normally on after successful download. 

U63   The DRAM uses an industry standard SIMM up to 16MB to provide for future function enhancements. 

82503 Dual Serial Transceiver (DST) 
29042104.pdf  
   The 82503 includes on-chip AUI and TPE drivers and receivers
82593, and 82596). This component incorporates six LED drivers to dis-
play transmit data, receive data, collision, link integrity, polarity faults and port selections, allowing for complete network monitoring by the user. The transmit, receive and collision LEDs indicate the rate of activity by the frequency of flashing.

82C54 CHMOS Programmable Interval Timer
23124406.pdf 
   Three independent 16-bit counters, each capable of handling clock
inputs up to 10 MHz. All modes are software programmable. The 82C54 is pin compatible with the HMOS 8254, and is a superset of the 8253. Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator, programmable one-shot, and in many other applications. 

82596CA High-Performance 32-Bit Local Area Network Coprocessor 
29021806.pdf 

ADVANCED ADAPTER TECHNOLOGY
   PeerMaster adapters employ a "deep" design (each adapter has its own processor), enabling the adapters to off-load selected LAN functions from the server processor.  The PeerMaster attaches to the MC bus with the "Miami" module, which supports 80MB/sec data-streaming mode and peer-to-peer data transfers across the MC.  The advanced channel interface enables 64-bit wide data transfers direct from adapter to adapter, with a performance improvement up to four times that of currently available Ethernet adapter alternatives. 

What is the card edge connector for? 

From Peter 
>Will this adapter work with Windows 95? 
No. All 4 adapters share 1 interrupt. 

>And will this device take the place of an external hub? 
No. It is a "4 single adapters on one card" ... not a hub. 

These adapters support: 
  40MB/sec data transfers between host PC and adapter 
  64-bit wide data transfers among ports on an adapter 
 80MB/sec data transfers among ports across multiple adapters with no host processor intervention 
 High performance means to forward cross-segment traffic without impacting server performance 
   64-bit data transfers across the Micro Channel at burst rates of 640Mbps, which equals the total bandwidth of 64 Ethernet ports (Only IF you have a 500 class system with six Peermasters!)

Device I/O Address
   The system bus I/O address of the adapter. 
  <1C00H-1C1FH>, 3C00H-3C1FH, 5C00H-5C1FH, 7C00H-7C1FH, 9C00H-9C1FH, BC00H-BC1FH, DC00H-DC1FH, FC00H-FC1FH 

Interrupt Level
   The prioritized interrupt request line on which the adapter interrupts the system. The interrupt level may be shared with another adapter. The highest to lowest interrupt priorities are: 
  <Level 3>, 4, 5 

Primary Arbitration Level
   Primary arbitration level for bus master direct memory access (DMA) transfers. An arbitration level of 1 has the highest priority; increasing levels have corresponding decreased priority. 
  <Level E>, D, C, B, A, 9, 8, 7, 6, 5, 4, 3, 2, 1 

Streaming Data
   Enables or disables the Streaming Data feature of the adapter as both a bus master and a slave. Disable causes the adapter to use the basic data transfer procedures. Streaming data procedure is supported when enabled. 
  <Disabled>, Enabled 

Selected Feedback Return
   Checks for and reports loss of selected feedback return by the bus master of the adapter. 
  <Disabled>, Enabled 

Address and Data Parity
   Enables or disables the address and data parity checking and generation by the adapter. 
  <Disabled>, Enabled 

First Shared Storage Window Location
   There are two independent windows into the random access memory (RAM) on the adapter. This is the first window that is located in the read-only memory (ROM) or RAM area. This window is  either 8KB or 16KB 

Note:  The second window is used for peer data transfers. The setup program automatically selects this window above the 1MB boundary in Micro Channel address space. For Model 85 setup instructions, see “Special Instructions for Model 85” below 

Special Instructions for Model 85
   To provide for peer data transfers, Quad PeerMaster adapters support a system bus window into their local memory. The location of this window is normally selected, verified, and reserved by the automatic configuration program during the adapter installation process. Due to limitations of the setup program provided on some IBM Model 85 servers, however, this window is not reserved by the automatic configuration program. Instead, the device driver provides a default window location for each installed Quad PeerMaster adapter. The default window location of each installed adapter is based upon the expansion slot of the adapter in the following manner: 
   Conflicts cannot be detected and resolved by the device driver. Use the setup program on your system to manually verify that conflicts do not exist with the default window locations. You may override the default window locations to resolve possible conflicts. The MEMORY keyword allows you to override the default values. This keyword specifies a system bus address for the adapter window base, as follows: 

:LOAD [PATH]MXMCA4BT.LAN  SLOT=11  MEMORY=N 
   N specifies a window base address in MB. Thus, a value of 100 meanss a base address of 100MB. Minimum value of  4, Maximum value of  255